Publications
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Books (Total Count = 00)
    None
Book Chapters (Total Count = 02)
  • A.J. Mondal, A. Majumder, B.K. Bhattacharyya, "Signalling Schemes for the Design of Low Voltage Swing Transceiver Circuit", Chapter – 3 for the Book titled VLSI and Post CMOS Devices, Circuits and Modelling by IET, 2018.
  • A. Majumder, S. Ghosh, J. Goswami, B.K. Bhattacharyya, "NFC in IoT Based Payment Architecture", Chapter – 9 for the Book titled The Internet of Things: Foundations for Smart City, E-Health and Ubiquitous Computing, by CRC Press, Taylor & Francis Group, 2017.
Journals/Letters/Magazines (Total Count = 30)
    Articles Under Review
  • A. Majumder, M. Das, B.K. Bhattacharyya, “Variation Aware Design Approach of Current Mode Single Ended Mux for High Speed Serializer Applications”, AEU-International Journal of Electronics and Communications, Elsevier.
  • Year: 2019
  • P. Bhattacharjee, D. Sarkar, A. Majumder, "A Variation Tolerant Data Dependent Clock Gating Approach for PSN Attenuated Low Power Digital IC", Ain Shams Engineering Journal, Elsevier, 2019.
  • Year: 2018
  • A. Majumder, M. Das, S.K. Saw, A.J. Mondal, B.K. Bhattacharyya, “Variation Aware Design of 50Gbit/s, 5.027fJ/bit Serializer using Latency Combined Mux-Dual Latch for Inter-Chip Communication”, IEEE Transactions on Circuits and Systems I: Regular Papers, Vol-xx, No-xx, 2018.
  • A. Majumder, M. Das, S.K. Saw, B.K. Bhattacharyya, “An Energy Efficient PVT Aware Novel CML-TG based Mux-Latch Circuit Serializes High Rate Data”, Microsystem Technologies, Springer, Vol-xx, No-xx, 2018.
  • P. Bhattacharjee, A. Majumder “A Variation Aware Robust Gated Flip-Flop for Power Constrained FSM Application”, Journal of Circuit, System and Computers, World Scientific Publishers, Vol-28, No-07, 2018.
  • A. Majumder, B. Nath, M. Das, B.K. Bhattacharyya, “A Variation Tolerant Current Mode Low Swing Signaling Approach for Gigascale On-chip Interface Circuit”, AEU-International Journal of Electronics and Communications, Elsevier, Vol-93, PP-140-149, 2018.
  • S.K. Saw, P. Das, M. Maiti, A. Majumder “A Power Efficient Charge Pump Circuit Configuration for Fast Locking PLL Application”, Microsystem Technologies, Springer, Vol-xx, No-xx, 2018.
  • A. Majumder, P. Bhattacharjee, T.D. Das “A Novel Gating Approach to Alleviate Power and Ground Noise in Silicon Chip”, Journal of Circuits, Systems and Computers, World Scientific Publishers, Vol-27, No-9, August 2018.
  • S. Rambabu, A. Majumder, “Gain Improved Design of Cascode OTA using PMOS Based Positive Feedback”, IEEE VLSI Circuit and System Letters Vol-4, Issue-2, May, 2018.
  • A. Majumder, P. Bhattacharjee “Variation Aware Intuitive Clock Gating to Mitigate On-chip Power Supply Noise”, International Journal of Electronics, Taylor & Francis, Vol-105, No-7, April 2018.
  • N. Laskar, S. Debnath, A. Majumder and B.K. Bhattacharyya, “A New Current Profile Determination Methodology Incorporating Gating Logic to Minimize the Noise of CPU Chip by 40%”, Journal of Circuit, System and Computers, World Scientific Publishers, Vol. 27, Issue 3, March 2018.
  • P. Bhattcharjee, A.J. Mondal, A. Majumder, “A graphical approach to design and optimization of MOS amplifier”, Journal of Engineering Science and Technology (JESTEC), Vol-13, No-01, 2018.
  • Year: 2017
  • A. Majumder, “Gated Clock Tree Circuit to Reduce the Noise in Silicon Chip”, Journal of Low Power Electronics, American Scientific Publisher, Vol-13, No-4, December 2017.
  • A. Majumder, A.J. Mondal, B.K. Bhattacharyya, “A 65nm Design of 0.6V/8.98µW PVT Aware Dynamic Analog Comparator for High Speed Data Reconstruction Applications”, ASP Journal of Low Power Electronics; Vol-13, No-3, September 2017.
  • B. Nath, A. Majumder, M. Das, A.J. Mondal, P. Chakraborty, B.K. Bhattacharyya, “Voltage Keeper Based 28.27µW New Frequency Divider Circuit in 90nm Technology for Gigascale SerDes Application”, IEEE VLSI Circuit and System Letters Vol-3, Issue-2, June 2017.
  • A. J. Mondal, A. Majumder, B.K. Bhattacharyya, P. Chakraborty, “A Process Aware Delay Circuit with Reduce Impact of Input Switching at GHz Frequencies”, IEEE VLSI Circuit and System Letters Vol-3, Issue-2, June 2017.
  • P. Bhattacharjee, A. Majumder, B. Nath, “A 23.52µW/0.7V Multistage Flip-flop Architecture steered by Leakage Control Transistor based Gated Clock”, IEIE Transactions on Smart Processing and Computing, Vol-6, No-3, June 2017.
  • A. J. Mondal, A. Majumder, B.K. Bhattacharyya, “Mathematical Formulation to Design and Implementation of a Low voltage swing transceiver circuit”, Integration, The VLSI Journal; Elsevier, Vol-58, pp. 356-368, June 2017.
  • A. Majumder, A.J. Mondal, B.K. Bhattacharyya, “Threshold Adjustment of Receiver Chip to Achieve a Data Rate > 66Gbit/s in Point-to-point Interconnect”, Integration, The VLSI Journal; Elsevier, Vol. 58, pp. 348-355, June 2017.
  • A. Majumder, B.K. Bhattacharyya, “Reconstruction of single pulse originally having 40psec width coming from a lossy and noisy channel in point to point interconnect”, Turkish Journal of Electrical Engineering and Computer Sciences Vol. 25, No. 03, PP. 2055 – 2065, May 2017.
  • A. Majumder, J. Goswami, S. Ghosh, R. Shrivastawa, S.P. Mohanty and B.K. Bhattacharyya, “Pay-cloak: A Biometric Back Cover for Smartphones: Facilitating Secure Contactless Payments and Identity Virtualization at Low Cost to the End Users “, IEEE Consumer Electronics Magazine, Vol. 6, Issue - 2, April 2017.
  • S. Ghosh, A. Majumder, J. Goswami, A. Kumar, S.P. Mohanty, B.K. Bhattacharyya, “Swing-Pay: One Card Meets All User Payment and Identity Needs: A Digital Card Module using NFC and Biometric Authentication for Peer-to-Peer Payment”, IEEE Consumer Electronics Magazine, Vol. 6, Issue - 1, January 2017.
  • Year: 2016 & Before
  • S.K. Singh, A.J. Mondal, A. Majumder, ‘’Generation and Performance Evaluation of Reconfigurable Fault Tolerant Routing Algorithm for 2D Mesh NOC”, 3rd International Conference on Recent Trends in Computing 2015, Elsevier.
  • A. Majumder, B. Chowdhury, P.L. Singh, R. Rai “Synthesis & Realization of N-bit Reversible Register File used in Bus Organization of Processor Architecture”, 3rd International Conference on Recent Trends in Computing 2015, Procedia Computer Science, Vol-57, pp – 305-312, Elsevier.
  • A. Majumder, P.L. Singh, B. Chowdhury, A.J. Mondal, V. Anand, “Efficient Design & Analysis of N-bit Reversible Shift Registers”, 3rd International Conf. on Recent Trends in Computing 2015, Procedia Computer Science, Vol-57, pp – 199-208, Elsevier.
  • P.L. Singh, A. Majumder, B. Chowdhury, A.J. Mondal, T.S. Shekawat, "Reducing Delay & Quantum Cost in the Novel Design of Reversible Memory Elements", 3rd International Conference on Recent Trends in Computing 2015, Procedia Computer Science, Vol-57, pp – 189-198, Elsevier.
  • A. Majumder, B. Nath, D. Sarkar, M. Das, “Cycle in Conventional Combinational Circuits: A Comprehensive Survey”, International Journal Advanced Science & Technology, Korea, Vol. 80, July 2015.
  • A. Kar, A. Majumder, “A 43µwatt 3-bit Flash ADC designed with TMCC and Bit Referenced Encoder in 180 nm CMOS Technology”, International Journal Advanced Science & Technology, Korea, Vol. 79, June 2015.
  • A. Majumder, “Design of an H-shaped Microstrip Patch Antenna for Bluetooth Applications,” International Journal of Innovation and Applied Studies, vol. 3, no. 4, pp. 987–994, August 2013.
  • A. Majumder, “Rectangular Microstrip Patch Antenna using Co-axial feeding technique to operate in S- Band”, International Journal of Engineering Trends and Technology, Vol. 4, Issue-4, pp. 1206 – 1210, April 2013.
  • A. Majumder, “A Design of RF – Based Programmable Frequency Divider for IEEE 802.11a Wireless Access”, IOSR Journal, Vol. 4, Issue 1, pp. 01-10, Nov – Dec 2012.
Conferences (Total Count = 41)
      Year: 2018
    • P. Bhattacharjee, A. Majumder, "A Variable Delay Circuit to Develop Identical Rise/Fall Time in the Output" Springer, 2nd International Conference on Computational Advancement in Communication circuit and System (ICCACCS-2018), 23 - 24th November 2018, Kolkata, India. (Best Paper Award)
    • D. Sarkar, P. Bhattacharjee, A. Majumder, “Data Dependent Clock Gating Approach for Low Power Sequential System”, 5th International Conference on Microelectronics, Circuits & Systems (MICRO - 2018), 19 - 20th May 2018, Bhubaneswar, India.
    • P. Das, S.K. Saw, M. Maiti, A. Majumder, “Low Power Fast Locking Charge Pump Architecture for PLL Application”, 5th International Conference on Microelectronics, Circuits & Systems (MICRO - 2018), 19 - 20th May 2018, Bhubaneswar, India.
    • S.K. Saw, M. Maiti, M. Jana, A.J. Mondal, A. Majumder, “A Current Mode VCO Design Approach for Higher Oscillation Frequency”, 5th International Conference on Microelectronics, Circuits & Systems (MICRO - 2018), 19 - 20th May 2018, Bhubaneswar, India.
    • S.K. Saw, M. Maiti, A. Majumder, “PVT Aware Design of a Dead-Zone Free High Speed Phase Frequency Detector in 90nm CMOS”, 5th International Conference on Microelectronics, Circuits & Systems (MICRO - 2018), 19 - 20th May 2018, Bhubaneswar, India.
    • Year: 2017
    • S.K. Saw, P. Das, M. Maiti, A. Majumder, “A 90nm Design of Charge Pump Circuit for Perfect Current Matching”, 6th International Conference on Computing, Communication and Sensor (CCSN - 2017), Kolkata, India.
    • M. Maiti, S.K. Saw, A. Majumder, “A 90nm Design of Low Power Voltage Controlled Oscillator with Wide Tuning Range”, 6th International Conference on Computing, Communication and Sensor (CCSN - 2017), Kolkata, India.
    • A. Majumder, M. Das1, S.K. Saw, B.K. Bhattacharyya, “Embedding of TG-CML to Design a Novel High Data Rate Multiplexer”, 6th International Conference on Computing, Communication and Sensor (CCSN - 2017), Kolkata, India.
    • M. Das, A. Majumder, A.J. Mondal, B.K. Bhattacharyya, “A 90nm Novel Mux-Dual Latch Design Approach for Gigascale Serializer Application”, 3rd IEEE International Symposium on Nano-electronic and Information Systems (iNIS - 2017), 18-20th December, Bhopal, India.
    • A. Majumder, P. Bhattacharjee, “Current Profile Generated by Gating Logic Reduces Power Supply Noise of Integrated CPU Chip”, 3rd IEEE International Symposium on Nano-electronic and Information Systems (iNIS - 2017), 18-20th December 2017, Bhopal, India. (Student Travel Grant from TC-VLSI, IEEE Computer Society, USA)
    • B. Nath, A. Majumder, “Binary Counter Based Gated Clock Tree for Integrated CPU Chip”, 3rd IEEE International Symposium on Nano-electronic and Information Systems (iNIS - 2017), 18-20th December 2017, Bhopal, India.
    • A. J. Mondal, A. Majumder, B.K. Bhattacharyya, “A Design Methodology for MOS Current Mode Logic VCO”, 3rd IEEE International Symposium on Nano-electronic and Information Systems (iNIS - 2017), 18-20th December 2017, Bhopal, India.
    • S. Rambabu, A. Majumder, A.J. Mondal, “A 90nm Gain Enhanced Modified Cascode OTA Structure with Positive Feedback Load”, IEEE International Conference on Communication and Electronics Systems (ICCES 2017), 19-20th October 2017, Coimbatore, India.
    • P. Bhattacharjee, B. Nath, A. Majumder, “LECTOR Based Clock Gating for Low Power Multi-Stage Flip Flop Applications”, IEEE & IEIE 16th International Conference on Electronics, Information, and Communication (ICEIC - 2017), Phuket, Thailand. (Best Paper Award)
    • Year: 2016
    • P. Bhattacharjee, A. Majumder, “LECTOR Based Gated Clock Approach to Design Low Power FSM for Serial Adder”, 2nd IEEE International Symposium on Nano-electronic and Information Systems (iNIS - 2016), 19-21st December, Gwalior, India.
    • P. Bhattacharjee, A. Majumder, T.D. Das, “A 90 nm Leakage Control Transistor Based Clock Gating for Low Power Flip Flop Applications”, IEEE 59th International Midwest Symposium on Circuit and System (MWSCAS - 2016), Abu Dhabi, UAE.
    • P. Bhattacharjee, A.J. Mondal, A. Majumder, “A Constraint Driven Technique For MOS Amplifier Design”, IEEE 20th International Symposium on VLSI Design and Test (VDAT-2016), IIT Guwahati, Assam, India.
    • R.P. Acharya, A.J. Mondal, A. Majumder, “A Method To Design A Comparator For Sampled Data Processing Applications”, IEEE 20th International Symposium on VLSI Design and Test (VDAT-2016), IIT Guwahati, India.
    • A. Majumder, M. Das, B. Nath, A.J. Mondal, B.K. Bhattacharyya, “Design of Low Noise High Speed Novel Dynamic Analog Comparator in 65nm Technology”, 26th Conf. on RADIOELEKTRONIKA 2016, Kosice, Slovakia.
    • R. Kaushik, A. Majumder, A.J. Mondal, “Design and Analysis of New Glitch Free Adiabatic Logic Circuits”, IEEE 26th International Conference on RADIOELECTRONIKA 2016, Kosice, Slovakia.
    • P. Bhattacharjee, A.J. Mondal, A. Majumder, “Amplifier Design and Optimization Using Non Linear Programming”, IEEE 26th International Conference on RADIOELECTRONIKA 2016, Kosice, Slovakia.
    • A. Majumder, P. Deb, S.K. Yadav, “Power and Energy Efficient Logic Design using Stacking Effect of Transistors”, IEEE International Conference on Electrical, Electronics and Optimization Techniques (ICEEOT 2016), Chennai, India.
    • P. Deb, A. Majumder, “Leakage Reduction Methodology of 1-bit Full Adder in 180nm CMOS Technology”, 3rd International Conference on Devices, Circuits and Systems, IEEE, Coimbatore, India, 2016.
    • A. Majumder, R. Kaushik, “Mathematical Modeling and Analysis of New Modified Glitch Free Adiabatic Inverter Circuit with Trapezoidal Power Supply” VLSI SATA 2016, Bangalore, India, Sponsored by IEEE.
    • Year: 2015 & Before
    • A. Majumder, A.J. Mondal, V. Chaudhary, B.K. Bhattacharyya, “A Methodology to Achieve Over 25Gbit/s data rate in Point to Point Interconnect”, 11th International conf. on Microwave, Antenna, Propagation & Remote Sensing, IEEE-GRSS, Jodhpur, India.
    • A. Majumder, B. Chowdhury, V. Chaudhary, P. Chakraborty, B.K. Bhattacharyya, “A Methodology of High Speed Signaling through strip-line Interconnect using Resistive Channel to Minimize ISI Noise”, 11th International conference on Microwave, Antenna, Propagation & Remote Sensing, IEEE-GRSS, Jodhpur, India.
    • A. Majumder, D.T. Reddy, R. Shrivastawa, “Generation of Chaos using a Simple Electronic Circuit”, International Conference on Applied and Theoretical Computing and Communication Technology (ICATCCT 2015), Karnataka, India.
    • A. Majumder, B. Chowdhury, V. Kumar, “Cost Efficient Realization & Synthesis of Reversible Pre-settable Program Counter for Processor”, International Conf. on Applied & Theoretical Computing and Communication Technology (ICATCCT - 2015), IEEE.
    • J. Goswami, S. Ghosh, A. Majumder, S. Katiyar, “Development of a Prototype to detect Speed Limit Violation for Better Traffic Management”, 8th International Conf. on Contemporary Computing (IC3-2015), IEEE, Noida, India.
    • A. Kar, M. Das, B. Nath, D. Sarkar, A. Majumder, “Comparative Analysis of Low Power Novel Encoders for Flash ADC in 45nm Technology”, IEEE International Conference on Smart Technologies and Management for Computing, Communication, Controls, Energy & Materials (ICSTM - 2015), Chennai, India.
    • M. Das, B. Nath, D. Sarkar, A. Kar, A. Majumder, “Design of Ultra Low Power Novel 3-Bit Flash ADC in 45nm CMOS Technology”, IEEE International Conference on Smart Technologies and Management for Computing, Communication, Controls, Energy & Materials (ICSTM - 2015), Chennai, India.
    • S. Ghosh, J. Goswami, A. Kumar, A. Majumder, “Issues in NFC as a form of Contactless Communication: A Comprehensive Survey”, IEEE International Conference on Smart Technologies and Management for Computing, Communication, Controls, Energy & Materials (ICSTM - 2015), Chennai, India.
    • D. Muchahary, A.J. Mondal, R.S. Parmer, A.D. Borah, A. Majumder, “A Simplified Design Approach for Efficient Computation on DCT”, 5th IEEE International Conf. on Communication System and Network Technologies (CSNT-2015), Gwalior, India.
    • A.J. Mondal, A.D. Borah, D. Muchahary, A. Majumder, “FIR Low Pass filter design using Craziness Base Particle Swarm Optimization Technique”, International Conf. on Communication and Signal Processing (ICCSP-2015), IEEE, Tamilnadu, India.
    • D. Muchahary, A.J. Mondal, A. Majumder, “A CORDIC Based Design Technique for Efficient Computation of DCT”, International Conference on Communication and Signal Processing (ICCSP-2015), IEEE, Tamilnadu, India.
    • A.J. Mondal, S.K. Singh, A. Majumder, "Generation and Performance Evaluation of Reconfigurable Random Routing Algorithm for 2D Mesh NOC", 16th IEEE Latin American Test Symposium (LATS 2015), Mexico.
    • P.L. Singh, A. Majumder, B. Chowdhury, R. Singh, N. Mishra, “A Novel Realization of Reversible LFSR for its Application in Cryptography”, 2nd International Conference on Signal Processing and Integrated Networks, Noida, India, Sponsored by IEEE.
    • A. Majumder, B. Chowdhury, A.J. Mondal, K. Jain, “Investigation on Quine McCluscky Method: A Decimal Manipulation Based Novel Approach for the Minimization of Boolean Function”, Proceedings of International Conference on EDCAV 2015, pp – 08 – 12, Shillong, India, Sponsored by IEEE.
    • K. Jain, S.K. Singh, A. Majumder, A.J. Mondal, “Problems Encountered in Various Arbitration Techniques used in NOC Router: A Survey”, Proceedings of International Conference on EDCAV 2015, pp – 124 - 129, Shillong, India, Sponsored by IEEE.
    • A. Majumder, P.L. Singh, N. Mishra, A.J. Mondal, B. Chowdhury, “A Novel Delay & Quantum Cost Efficient Reversible Realization of (2i x j) Random Access Memory”, IEEE VLSI SATA 2015, Bangalore, India.
    • A. Kar, A. Majumder, A.J. Mondal, N. Mishra, “Design of Ultra Low Power Flash ADC using TMCC & Bit Referenced Encoder in 180 nm Technology”, IEEE VLSI SATA 2015, Bangalore, India.